Digital-to-analog converter

ABSTRACT

A DIGITAL-ANALOG CONVERTOR INCLUDING A REGISTER, A RESISTIVE NETWORK, AND AN AMPLIFIER CIRCUIT. THE REGISTER INCLUDES A FIRST SET OF FLIP-FLOPS THAT PROVIDES DIGITAL OUTPUT SIGNALS IN A REPETITIOUS, ASCENDING ORDER, BINARY COUNT SEQUENCE AND A SECOND SET OF FLIP-FLOPS THAT PROVIDES INDIVIDUAL OUTPUT SIGNALS CORRESPONDING TO THE INDIVIDUAL REPETITIONS OF THE FIRST SET OF FLIP-FLOPS. THE RESISTIVE NETWORK INCLUDES A PLURALITY OF BINARY WEIGHTED RESISTORS THAT ARE COUPLED TO RECEIVE THE OUTPUT SIGNALS PROVIDED BY THE FIRST SET OF FLIP-FLOPS AND A PLURALITY OF EQUALLY WEIGHTED RESISTORS THAT ARE COUPLED TO RECEIVE THE OUTPUT SIGNALS PROVIDED BY THE SECOND SET OF FLIP-FLOPS. ALL BUT ONE OF THE BINARILY WEIGHTED RESISTORS HAVE A COMMON OUTPUT TERMINAL FOR PROVIDING A FIRST SUMMING SIGNAL AND ALL OF THE EQUALLY WEIGHTED RESISTORS AND ONE OF THE BINARILY WEIGHTED RESISTORS HAVE A COMMON OUTPUT TERMINAL FOR PROVIDING A SECOND SUMMING SIGNAL. AN AMPLIFIER CIRCUIT IS COUPLED TO RECEIVE THE FIRST SUMMING SIGNAL AND THE SECOND SUMMING SIGNAL FOR PROVIDING AN ANALOG OUTPUT SIGNAL BEING DIFFERENTIALLY RELATED TO THE RECEIVED SUMMING SIGNALS.

United States Patent [72} Inventor John A. Propmer Primary Examiner-Maynard R. Wilbur La Mirada, Calif. Assistant Examiner.leremiah Glassman [21] Appl. No. 847,089 AuarneysJames K. Haskell and Bernard P. Drachlis [22] Filed Aug. 4, 1969 [45] Patented June 28, 1971 73 Assign H h Air raft Company ABSTRACT: A digital-to-analog converter including a re- Culver City, Calif. gister, a resistive network, and an amplifier circuit. The register includes a first set of flip-flops that provides digital output signals in a repetitious, ascending order, binary count sequence and a second set offiip-flops that provides individual output signals corresponding to the individual repetitions of I 54] DIGITAITGANALOG CONVERTER the first set of flip-flops. The resistive network includes a plu- 12 clams, 2 Drawing Figs. rahty of binary welghte d resistors that are coupled to recelve the output signals provided by the first set of flip-flops and a [521 340/347 plurality of equally weighted resistors that are coupled to [51] Int. Cl ..H03k 13/02, receive the output signals provided by the second Set f fIIp 13/04 flops. All but one of the binarily weighted resistors have a [50] Field of Search 340/347 common output terminaI f providing a first Summing SIgnaI v and all of the equally weighted resistors and one of the binarily [56] References (med weighted resistors have a common output terminal for provid- UNITED STATES PATENTS ing a second summing signal. An amplifier circuit is coupled to 3,366,947 1/1968 Kawashima 340/347 receive the first summing signal and the second summing 3,372,265 1963 r n 340/ 47 signal for providing an analog output signal being dif- 3,403,393 9/1968 Skrenes 340/347 ferentially related to the received summing signals.

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BACKGROUND OF THE INVENTION This invention relates, in general, to a digital-to-analog converter and, more particularly, to a digital-to-analog converter for minimizing errors in the output signal due to switching transients.

Heretofore, to convert a binary number to an analog signal resistor, divider networks have been coupled to receive output signals provided by a register having a plurality of stages of memory elements, or flip-flops, which store a digital number. The resistor divider network includes a plurality of resistors that can be weighted so that the output of each of the stages in the register will contribute to the output voltage in proportion to the binary weight of ,individual resistors in the resistor network. This binary signal to the divider network determines the value of the analog output signal, since the divider network is a passive element. However, because digital voltage levels are not usually as precise as required in an analog system, level amplifiers, or switches, are generally placed between the register and the divider network. The level amplifiers, or switches, switch the output of individual resistors in the divider network between ground and a reference voltage.

The digital-to-analog converter output can contain transients, if many bits change stages simultaneously. For example, in switching from a binary number, such as 01 l l, to a binary number 1000, all of the flip-flops in the register change state. Even though the corresponding two values of the analog voltage are very close, the transients occur on the resistor divider output for the following reasons: variation in transient times of the flip-flops; transient current draw from the reference supply; the fact that the flip-flops have a slower fall time than rise time; and the fact that the signals must propagate through the divider network. The largest error due to switching is generally from midscale to one count less or from one count below midscale to midscale.

SUMMARY OF THE INVENTION An object of this invention is to provide an improved digitalto-analog converter that has the advantage of substantially reducing errors in output signals due to the changing of electrical state of the components.

Another object of this invention is to provide an improved digital-to-analog converter that has the advantage of eliminating the requirement for precision switches.

The above and other objects of this invention can be attained by a circuit including a register, a resistive network and an operational amplifier. The register is coupled to receive logic input signals and clock pulse signals for providing digital output signals in response to the received signals. The register includes a plurality of memory elements, or flip-flops, that can be selected to have substantially the same turnofi times and have substantially the same turn-on times and which are individually coupled to receive the logic input signals and the clock pulse signals for providing digital output signals. A first set of flip-flops provides digital output signals in a repetitious, ascending order, binary count sequence from a first repetition to an nth repetition. Individual ones of a second set of flipfiops provide an output signal at the cessation of the individual repetitions of the first set of flip-flops.

The resistive network includes a plurality of binary weighted resistors and a plurality of equally weighted resistors and a bias resistor. The plurality of binary weighted resistors are individually coupled to receive the output signals provided by all but one of the flip-flops of the first set of flip-flops. The plurality of equally weighted resistors are individually coupled to receive individual output signals provided by the second set of flip-flops and the output provided by one of the flip-flops of the first set of flip-flops. The outputs of the all but one of hinary weightcd resistors are coupled together for providing a first summing signal related to the accumulated binary weight of the binary weighted resistors receiving digital signals from the register. The output set of equally weighted resistors and one of the binary weighted resistors and the bias resistor are coupled together for providing a second summing signal related to the accumulative weight of the resistors receiving a digital signal from the register and the bias register.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings wherein like reference characters designate like or corresponding parts, there is shown in FIG. I a register I0, a resistive network 20 and an operational amplifier 30.

The register 10 includes a plurality of memory elements, or flip-flops, Ila-12:: (where n is any integer representing an nth stage) that are individually coupled to receive clock pulse signals, CP, at a clock input terminal C and logic signals L at a J and a K input terminal for providing digital output signals in response to the received signal. The outputs of flip-flops 12a- 12c and lZe are provided by the O output terminal, and the outputs of the flip-flops 12d and IZf-IZn are provided by the Q output terminal.

The plurality of flip-flops l2a-l2n can be .l-K flip-flops, such as SHUL II, SFl l0/l30 J-K flip-flops that are manufactured by Sylvania and described in their report, New Product Report, June I, I967. .l-K flip-flops of the type referred to above operate such that the 0 output of the flip-flop will change from the high state to the low state if the J input terminal is high and a clock pulse signal is received, and from the low state to the high state if the K input terminal is high and a clock pulse signal is received. The above-described and other logic is illustrated by the following truth table:

The above-referenced flip-flops can have a turnoff delay when the output of the flip-flop changes from the zero, or low state, to the one, or high state, and a turn-on delay when the output of the flip-flops change from the one, or high state, to the zero, or low state. The turnoff delay is the duration oftime from the time a negative-going edge ofa clock pulse signal CP is received until the output changes from the minimum output value to the maximum output value. The turn-on delay is the duration of time from the time a negative-going edge of a clock pulse signal is received until the output changes from the maximum output value to the minimum output value. The turnoff delay is generally shorter in duration than the turn-on delay. Furthermore, the plurality of flip-flops I2a- [2n can be selected to have the same turn-on delay and the same turnoff delay. However, the turnoff delay and the turn-on delay cannot be precisely equal under the present manufacturing techniques.

One output of each of the plurality of flip-flops 12a-l2n is further coupled to a positive voltage terminal +v through individual coupling or pullup resistors l4al4n for coupling and decoupling the outputs between ground and the positive voltage terminal. When using flip-flops of the type referred to above, when the output of an individual one of the plurality of flip-flops l2a-l2n is low, the positive voltage +v is effectively coupled to ground through the respective flip-flop. However, when the output of an individual one of the plurality of flipflops is high, the positive voltage is decoupled from ground and provides an output signal approximately equal to the positive voltage +v. The applying of the positive voltage +v to the output of the individual flip-flops 12a-l2n through the individual coupling resistors l4a-l4n has the advantage of eliminating the need for precision switches between the output of the register 10 and the resistive network 20 by providing a constant voltage at the outputs of the flip-flops l2a12n when the outputs are high to eliminate internal variations of the particular flip-flops.

The resistive network 20 includes a plurality of binary weighted resistors 22a-22e, a plurality of equally weighted resistors 22f-22n and a bias resistor 24. Each of the weighted resistors 220-2211 has a first end coupled to one output ofindividual ones of the plurality of flip-flops l2a-l2n and a second end connected together in two separate groups. A first group of resistors including binary weighted resistors 220- 22c and 22e have their first end coupled to the 6 output of flip-flops 120-120 and 12e, respectively, and have the second end coupled together in common circuit relationship to provide a first summing signal S, equal to the summation of the first group of the received signals. A second group of resistors, including binary weighted resistor 22d and equally weighted resistors 22f-22n and 24, have their first and coupled to the Q output of flip-flops l2dand 12f12n, and have their second end coupled together in common circuit relationship to provide a second summing signal S equal to the summation of the second group of the received digital signals. In addition, a bias resistor 24 has a first end connected to a bias voltage and a second end connected in common circuit relationship with the second ends of the second group of resistors 22d and 22f22n Binary weighted resistors 22a-22e are weighted to provide output signals at their second end having values related to a binary weight of l, 2, 4, 8, and I6, respectively, in response to digital output signals provided by flip-flops 12a-I2e. For example, the output of the resistors 22a-22e can be 0.015 v., 0.030 v., 0.060 v., 0.12 v. and 0.24 v., respectively. The equally weighted resistors 22f-22n are weighted to provide individual output signal having a value related to a binary weight of 32 in response to receiving the digital output signal from individual ones of flip-flops l2f-12n. For example, the

output of individual ones of the flip-flops 12f-12n can be 0.32 v. The bias resistor 24 is weighted to provide an output signal related to a binary weight of 23. For example, the output ofthe bias resistor 24 can be 0.23 v.

The operational amplifier 30 is coupled to receive the first summing signal S, and the second summing signal S, for providing an output signal having a value related to the voltage difference between the received signals. operationally, the inverting input of the operational amplifier is maintained either equal to or more positive than the noninverting input by either increasing the value of the second summing signal S, or by decreasing the value of the first summing signal S, or both.

The operational amplifier 30 can be a A709 HIGH PER- FORMANCE OPERATIONAL AMPLIFIER, manufactured by Fairchild Semiconductor Corporation and described in their handbook, "Fairchild Semiconductor Linear Integrated Circuits Handbook," 1967, pages 57 through 72.

An operational amplifier of the type referred to above has an inverting input and a noninverting'input and operates such that if a positive voltage is applied to the inverting input a negative output signal will be produced, while apositive voltage signal applied to the noninverting input produced a positive output signal. Furthermore, if the amplifier is operated having signals applied to both the inverting input and the noninverting input it will provide an output signal related to the voltage difi'erence between the received signals.

Referring now to the operation of the circuit illustrated in FIG. 1 and to the waveforms illustrated in FIG. 2, the plurality of flip-flops l2a-l2n provide output signals according to the following truth table in response to the corresponding input signal.

Input 8 1 1 Qm Q12! Qm Qua Q12 Q1211 Q11- 0- 1 O 1 1 1 0 -O 1 O 1 l 0 0 1 0 1 0 1 0 0 1 0 I 0 Input Signal Q1211 Q12: Q12. Qua Qm Q1212 Q12- l5 0 0 1 I O 0 0 1g o 0 o 0 1 1 1 11 0 0 0 l) 1 1 0 The flip-flops 12a- 12a provide output signals in a repetitious, ascending order, binary count sequence, as illustrated in FIGS. 2A-2E in response to receiving corresponding logic signals. The flip-flops 12f12n provide an output signal each time the output of the flip-flops 12a-12e counts from a binary 0 to a binary 32 and begins a new repetition after the first repetition. The voltage developed across the inverting input and noninverting input of the operational amplifier 30 for one repetition of the binary count 32 and possible errors that may be developed between the inverting input and noninverting input because of the turn-on delays of the flip-flops l2a-12f is illustrated in FIG. 2G. The waveforms of FIGS. 2A--2F further illustrate the tum-on delay of the outputs of the flip-flops 12a-l2f when the output signals change from a high state to a low state.

For an all binary zero input signal to the register 10, the flipflops 12f-l2n and 12d provide no output signal and the outputs of the flip-flops l2a-l2c and He are high and provide output signals which are applied to the binary weighted resistors 22a22c and 22e, respectively, in the resistive network 20 which, in turn, provides the first summing signal S, having a binary weight of 23. The first summing signal S, which is applied to the noninverting input is balanced by a voltage having a binary weight of 23 provided by the output of the bias resistor 24 which is applied to the inverting input of the operational amplifier 30, resulting in a zero voltage difference between the inverting input and the noninverting input Accordingly, when there is zero voltage difference between the inverting input and the noninverting input of the operational amplifier 30, a zero output voltage e, will result. The output voltage e, of the operational amplifier for a binary zero input signal can be represented by the follow- I The sequence of providing output signals from one of the flipfiops l2f-l2n is repeated with the initiation of each repetition of the count from a binary one to a binary 31 of the output of the flip-flops 12al2e until all of the flip-flops 12f- 12n provide an output signal. When an output signal is being provided by the output of all of the flip-flops l2fl2n,

when the next clock pulse is received. the outputs of all of the plurality of flip-flops l2a-12n return to the initial state for a binary zero, and the count sequence repeats.

Neglecting errors due to the turn-on time of the outputs of the't'lip-fiop 120, no errors in output signal will result, as long as the outputs of all of the plurality of flip-flops 22a-22n change state in the same direction; that is, all the outputs change from the low stage to the high state, or from the high state to the lowstate. However, when the outputs of some of the plurality of flip-flops IZa-lZn change to a high state, and the output of at least one of the plurality of flip-flops 12a- 12n changes from a high state to a low state, an errorin the output signal may result for a short duration of time, due to the differences in tumoff times and turn-on times of the respective flip-flops, as illustrated in FIG. 2G. For example, at the initiation of a binary 4, 12, 20... an error will result, due to the turn-on delay of the output of the flip-flop 12e, and at the initiation ofa binary 16, 32 an error will result due to the turn-on delay of the output of the flip-flop 12d.

The largest error that may result will be at the initiation of the binary l6 and at the initiation of a binary 32 and multiples thereof, as illustrated in FIG. 26. At the initiation of a binary 16, the output of the flip-flops l2a-12c change from a low state to a high state and the outputs of the flip-flops 12d and l2e change form a high state to a low state. Consequently, the output of the flip-flops 12d and l2e have a turn-on delay and the output of the flip-flops 12d and 12c will remain high for a short duration of time while the outputs of the flip-flops 12a- 12c are high. As a result, a negative error equivalent to eight least significant bits (LSB) may result. This error will be present until the outputs of the flip-flops 12d and 122 change to the low state.

When the binary input signal increases from a binary 31 to a binary 32, the outputs of the flip-flops l2al2c and 122 and the flip-flop 12f change from a low state to a high state and the output of the flip-flop 12d changes from a high state to a low state. Accordingly, the output of the flip-flop 12d will remain high for a short duration of time, while the outputs of the flipflops l2a-l2c and Re are high and an output error of positive eight least significant bits (LSB) may result until the output of the flip-flop 12d changes to the low state, as illustrated in FIG. 20.

As illustrated in FIG. 20, when the input signal changes from a binary 31 to a binary 32, the outputs of the flip-flops 12dl2 return to their initial setting for a binary zero input signal and the second summing signal S is comprised of the output of flip-flop 12f and the bias voltage signal and the first summing signal S is comprised of the outputs of the flip-flops 12a- 12 and 122.

As the binary number input signal increases, the operation of the circuit of FIG. 1 is repeated for each repetition of an increase of 3l (LSB) in the binary input signal. The largest error that will result will be an eight least significant digit error. If conventional digital-to-analog converter techniques are used, larger errors could result. For example, if a digit binary number is converted byconventional means, from a binary 5ll orOllllllllI to abinary 512 or 1000000000, an error of Sl 1 least significant digits could result because the nine bits that are changing from a binary one to a binary zero will have a tum-on delay which will cause them to remain in the high state for a short duration of time when the most significant bit is changing from a binary zero to a binary one.

While the salient features have been illustrated and describedwith respect to a particular embodiment, it should be readily apparent that modifications can be made within the spirit and scope of the invention.

lclaim:

1. A digital-to-analog converter, comprising:

a first set of memory elements, each of said first set of memory elements being coupled to receive logic input signals for providing digital output signals in a repetitious ascending order binary sequence in response to the received logic input signals; second set of memory elements, individual ones of said second set of memory elements being coupled to receive logic input signals for providing output signals at the cessation of the individual repetition of the output signals of said first set of memory elements; plurality of binary weighted resistors, individual ones of said plurality of binary weighted resistors having a first by individual ones of said first set of memory elements and having a second end connected together for providing a first summing signal related to the summation of the binary weight of said plurality of binary weighted resistors receiving digital output signals;

a plurality of equally weighted resistors, individual ones of said plurality of equally weighted resistors having a first end coupled to receive the output signal provided by individual ones of said second set of memory elements and having a second end connected in common circuit relationship with at least one of said binary weighted resistors for providing a second summing signal related to the summation of the individual equally weighted resistors and the binary weighted resistor receiving the digital signals; and

means coupled to said weighted resistors and responsive to said first and said second summing signals for providing an output signal being a function of the difference between the magnitude of said summing signals. 2. The digital-to-analog converter of claim 1 that further includes a plurality of coupling resistors, individual ones of said plurality of coupling resistors having a first end coupled to the first end of individual ones of the plurality of weighted resistors and a second end coupled to a voltage source.

3. The digital-to-analog converter of claim 1 in which each of said plurality of memory elements are J-K flip-flops.

4. The digital-to-analog converter of claim 2 in which said memory elements are J-K flip-flops.

5. The digital-to-analog converter of claim 3 in which said J-K flip-flops have substantially the same turn-on delay and substantially the same turnoff delay.

6. The digital-to-analog converter of claim 4 in which said J-K flip-flops have substantially the same turn-on delay and substantially the same turnoff delay.

7. The digital-to-analog converter of claim 1 in which said means coupled to said weighted resistors for providing output signals is an operational amplifier.

8. The digitaI-to-analog converter of claim 2 in which said means coupled to said weighted resistors for providing output signals is an operational amplifier.

9. The digital-to-analog converter of claim 3 in which said means coupledto said weighted resistors for providing output signals is an operational amplifier.

10. The digital-to-analog converter of claim 4 in which said means coupled to said weighted resistors for providing output signals is an operational amplifier.

11. The digital-to-analog converter of claim 5 in which said means coupled to said weighted resistors for providing output signals is an operational amplifier.

12. The digital-to-analog converter of claim 6 in which said meanscoupled to said weighted resistors for providing output signals is an operational amplifier.

3 3 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,588,882 Dated June 28, 1971 Inventor) John A. Propster It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

should be Col 5, line 62, "l2a-l2" should be -l2al2e-; line 65, "l2a-l2" should be -l2al2c.

Signed and sealed this 26th day of September 1972.

(SEAL) Attest:

ROBERT GOTISCHALK EDWARD M.FLETCHEH,JR.

Commissioner of Patents Attesting Officer 

